1. Field of the Invention
This invention relates to data communications in a computer system, and more specifically, to sequencing misaligned memory accesses forming misaligned bus transactions between a microprocessor and an external bus.
2. Art Background
In several conventional bus architectures, data transactions between the microprocessor and an external bus are permitted to start at any memory address with no alignment restrictions. This may result in requests issued to the external bus for memory accesses being split across at least two data bus width boundaries (i.e. each data bus being 8 bytes wide). Since the bus protocols for such microprocessors define a cache line data chunk return ordering which is not sequential with respect to the memory addresses (i.e., 8 bytes long), these processors must be able to sequence a misaligned memory access as two separate bus transactions in order to be compatible with the protocol of the external bus.
Conventional bus architectures have implemented sequencers for handling misaligned bus transactions. These sequencers take the original external bus request for the misaligned transaction issued by the microprocessor and split them into multiple requests, each of which represent a single transaction on the external bus that is within its data bus boundary width. Nonetheless, when an error occurs in processing of one of the split requests, the entire, original bus request must be canceled since no mechanism exists in such architectures for maintaining the ordering of the completion of the split requests so that a failed split request can be retried and completed in the order of its issuance.
This problem becomes even more significant for bus architectures and protocols in which the bus requests are to be issued and completed in-order on the external bus. This is because a misaligned bus transaction which must be canceled and reissued due to an error in processing of one of the split requests will cause a delay in the completion of other pending bus transactions that were issued subsequent to the canceled transaction, thereby resulting in a substantial performance penalty to the microprocessor.
Accordingly, it is an object of the present invention to provide an external bus micro-request sequencer for sequencing misaligned bus transactions comprising separate split requests in which the order of completion of the corresponding split requests is guaranteed.
It is another object of the present invention to provide a method and apparatus for sequencing misaligned bus transactions in a pipelined bus protocol wherein cancellation of the entire transaction due to an error in its corresponding split requests is avoided by preventing subsequent split and non-split requests from being serviced until the erred split request is guaranteed to complete.